| 引用本文: | 屈克庆,高 畅,许跃成,等.高渗透率下计及并网逆变器动态性能的新型锁相环设计方法及鲁棒性分析[J].电力系统保护与控制,2025,53(14):69-79.[点击复制] |
| QU Keqing,GAO Chang,XU Yuecheng,et al.Design method and robustness analysis of a novel phase-locked loop considering the dynamic performance of grid-connected inverters under high penetration[J].Power System Protection and Control,2025,53(14):69-79[点击复制] |
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| 摘要: |
| 针对高渗透率下并网逆变器输出阻抗与电网阻抗之间相互耦合引发系统稳定性和动态性能下降的问题，从优化锁相环控制结构角度考虑，提出一种基于前馈补偿的新型锁相环设计方案。首先，建立考虑锁相环影响的并网逆变器输出阻抗模型，基于此模型对传统锁相环和惯性锁相环特性进行分析，结果表明二者在弱电网下面对电网扰动时系统的动态和稳态性能均有所下降。为解决上述问题，通过对闭环系统零极点进行合理配置，推导出基于前馈补偿的新型锁相环结构小信号模型，同时给出参数设计方法并对其系统性能进行详细分析。分析表明，所提新型锁相环能够在提供附加惯性与阻尼的同时提升系统鲁棒性，有效解决弱电网下锁相环引起的系统稳定性与动态性能下降的问题。最后，通过RT-LAB硬件在环实验验证所提新型锁相环设计方案的有效性。 |
| 关键词: 高渗透率 并网逆变器 新型锁相环 零极点配置 鲁棒性 |
| DOI：10.19783/j.cnki.pspc.240856 |
| 投稿时间：2024-07-04修订日期：2024-10-11 |
| 基金项目:国家自然科学基金项目资助(52177184) |
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| Design method and robustness analysis of a novel phase-locked loop considering the dynamic performance of grid-connected inverters under high penetration |
| QU Keqing1,GAO Chang1,XU Yuecheng1,ZHAO Jinbin2,MAO Ling1,ZENG Zhiwei1 |
| (1. College of Electrical Engineering, Shanghai University of Electric Power, Shanghai 200090, China;
2. Offshore Wind Power Research Institute, Shanghai University of Electric Power, Shanghai 200090, China) |
| Abstract: |
| To address the issue of system stability and dynamic performance degradation caused by the coupling between the output impedance of grid-connected inverters and grid impedance under high renewable energy penetration, a novel phase-locked loop (PLL) design method is proposed based on feedforward compensation from the perspective of optimizing PLL control structure. First, the output impedance model of the grid-connected inverter considering the influence of the PLL is established. Based on this model, the characteristics of traditional PLL and inertia-based PLL are analyzed. The results reveal that both types exhibit deteriorated dynamic and steady-state performance under weak grid conditions when subjected to grid disturbances. To solve the aforementioned issue, a small-signal model for the novel PLL structure based on feedforward compensation is derived through appropriate pole-zero placement of the closed-loop system. A parameter design method is provided, and a detailed analysis of the system’s performance is conducted. The analysis indicates that the proposed novel PLL enhances system robustness while providing additional inertia and damping, effectively addressing the system stability and dynamic performance degradation issue caused by PLL under weak grid conditions. Finally, the effectiveness of the proposed novel PLL design is validated through hardware-in-the-loop (HIL) experiments using RT-LAB. |
| Key words: high penetration grid-connected inverter novel phase locked loop zero-pole configuration robustness |
