With the increase of the distributed power grid-connected, the grid is facing many problems, such as voltage disturbance, DC offset, unbalanced voltage, harmonic distortion and so on. The traditional Phase-Locked Loop (PLL) technique finds it hard to detect the frequency and phase of grid voltage quickly and accurately under such complex grid conditions. To this end, a new PLL (DDM-QT1-PLL) is proposed, adding additional filtering stages consisting of Delay Signal Cancelation (DSC) and Moving Average Filter (MAF) into the Quasi-Type-1 PLL (QT1-PLL). It is constructed to meet the grid-connected demand in complex grid conditions. αβDSC2 and dqDSC4 cascaded MAF are adopted as the out-loop and in-loop filtering in DDM-QT1-PLL to eliminate grid voltage DC offset, unbalanced and harmonic components, as well as to effectively improve the response speed and stability margin of the PLL system. A feed forward path is designed to compensate the phase error caused by αβDSC2 when the grid frequency drifts. Simulation results show that DDM-QT1-PLL has a fast response speed and provides a good disturbance rejection capability, and achieves a zero steady-state error under DC offset of non-nominal frequency. This work is supported by National Natural Science Foundation of China (No. 61763040), Ningxia Key Research and Development Program (Special Talents) (No. 2018BEB04003) and The Third Batch of Ningxia Youth Talents Supporting Program (No. TJGC2018095).