Constructing SMV network of intelligent substation process layer with switches has been becoming a fashion. This structure is convenient to share information among multiple devices, but it leads to uncertainty and indeterminacy in terms of time delay when transmitting in the network. This drawback requires a reliable time resource to realize synchronization, and the merging unit should have the ability of time keeping to a certain degree. To solve these problems, this paper gives a structure of switch based on FPGA aiming to measure the time delay of SMV packets transmission, and proposes a scheme of measuring and storing the time delay using the reserved bytes in IEC 61850-9-2 frame. FPGA realization and experiments justify the proposed structure and scheme of the time delay measurement.