To deal with the accuracy problem of Power Hardware-In-the-Loop (PHIL) simulation for Modular Multilevel Converter-based HVDC (MMC-HVDC) caused by the power interface hardware, a phase-lead correction unit that simulates an first-order high-pass RC filter is designed for time delay compensation. In this paper, the MMC is modeled with Thevenin's equivalent circuit to derive the real time value of damping impedance for SDIM interface and reduce the calculation burden. The SDIM-ITM interface is adopted for MMC-HVDC PHIL simulation, where ITM interface acts as a driver and SDIM interface acts as an observer, and it shows high accuracy and stability under conditions of both change of operating point and fault. However, the physical simulation accuracy is influenced by the interface (or power amplifier) time delay. Thus the phase of AC voltage signal exciting power amplifier is compensated by the proposed phase-lead correction unit to further improve the physical simulation accuracy. The effectiveness of the proposed time delay compensation method is verified by simulation results. This work is supported by National Key Research and Development Program of China (No. 2016YFB0900903) and Science and Technology Development Plan of Jilin Province (No. 20160307014GX).