This paper introduces the features of high real-time performance, high precision, and high reliability of FPGA in merging unit function implementation. It mainly introduces the point-to-point SV message sending and receiving method by adopting FPGA. The method and the principle of realizing merging unit time synchronization and punctuality via FPGA. In the process of point-to-point SV sending and receiving, FPGA controls DM9000C, caches the received message of SV in FIFO, and marks the time scale of the received message through the internal timer. During the interval of SV message receiving, FPGA, cooperating with the CPU, controls SV packet delivery time precisely, and guarantees its discreteness not more than 100 ns. In synchronism state, B code and 1588 time synchronization information are parsed through FPGA to accurately keep time synchronized of the merging unit, and the following algorithm is used to record the interval of second pulse time. When the external synchronization signal is lost, FPGA time synchronization module will be switched to punctuality state, which can keep punctuality precision of merging unit in a long time.