Synchronous sampling test contains data synchronization test and sample value accuracy test, which is one of the most important indicators of the merging unit. The status quo of the merging unit synchronous sampling test and technical difficulties are firstly analyzed, and then a specific implementation method of the merging unit synchronous sampling test device based on real-time Linux system, real-time FPGA subsystem and scalable interface signals is introduced. In order to achieve the scalability of the interface and meet the merging unit’s flexible input and output signals demand, this method uses FPGA I/O pins to construct a signal interface bus and assign FPGA pin functions through reading information saved by I2C bus EEPROM in the signal interface board. Also, this method realizes many functions like sample values receiving, time scale recording, sample values generating and transmitting, and simulating the direct communication between MII interface and the PHY in single chip FPGA. The results show that the test device can accurately reflect the synchronous sampling accuracy and data synchronization of the merging unit, so it has a strong practical value.