用于就地化保护关键技术的SoC设计

于同伟; 丁岳; 李良; 王峥

引用本文:	于同伟,丁岳,李良,等.用于就地化保护关键技术的SoC设计[J].电力系统保护与控制,2019,47(21):150-155.
	YU Tongwei,DING Yue,LI Liang,et al.SoC design for key technologies of outdoor installation protection[J].Power System Protection and Control,2019,47(21):150-155

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用于就地化保护关键技术的SoC设计
于同伟¹,丁岳²,李良²,王峥²
(1.国网辽宁省电力有限公司电力科学研究院，辽宁沈阳 110000;2.北京智芯微电子科技有限公司 (国家电网公司重点实验室、电力芯片设计分析实验室)，北京 100192)

摘要:

以解决变电站继电保护中存在因多个功能芯片导致的系统可靠性降低、运维难度增大为目的，提出了基于双核Cortex-A9的自研智能就地化保护SoC芯片。该芯片通过采用基于节点冗余算法的HSR环网结构，确保环内任何一个元件或链路阻塞时，报文均能沿另一方向传递至主机。使用多采样率多通道的动态可重构ADC采集模块，使芯片可以根据不同实时性要求进行软件修改。采用时钟数据恢复对FT3码流进行处理，以提高信息传输的可靠性。在UMC55工艺下，完成了该芯片的版图设计，芯片面积为5.3×5.3 mm，主时钟频率可达到500 MHz。仿真结果验证了所提出芯片的可行性和先进性。

关键词: 智能变电站就地化保护 SoC HSR环网可重构ADC 时钟数据恢复

DOI：10.19783/j.cnki.pspc.181484

分类号:

基金项目:国家电网公司科技项目资助(5222LK17001F)

SoC design for key technologies of outdoor installation protection

YU Tongwei¹,DING Yue²,LI Liang²,WANG Zheng²

(1. Electrical Power Research Institute of Liaoning Electric Power Co., Ltd., Shenyang 110000, China;2. State Grid Key Laboratory of Power Industrial Chip Design and Analysis Technology, Beijing Smart-Chip Microelectronics Technology Co., Ltd., Beijing 100192, China)

Abstract:

In order to solve the deterioration in system stability and the increase in difficulty of operation and maintenance caused by multiple functional chips in substation relay protection, this paper proposes a self-developed SoC chip for intelligent outdoor installation protection based on a dual-core Cortex-A9. First, the chip adopts the HSR ring network structure based on the node redundancy algorithm to ensure that when any component or link in the ring is blocked, message will still be transmitted to the host in another direction. Then, with a multi-rate multichannel dynamic reconfigurable ADC acquisition module in the chip, the software of chip can be modified according to different real-time requirements. Besides, clock data recovery is used to process FT3 code stream to improve the reliability of information transmission. The floorplan and layout design of chip are presented through UMC55 CMOS process. The total area is 5.3 × 5.3 mm and the main clock frequency can reach 500 MHz. The proposed chip is verified to be feasible and advanced through simulation results. This work is supported by Science and Technology Project of State Grid Corporation of China (No. 5222LK17001F).

Key words: intelligent substation outdoor installation protection SoC HSR net reconfigurable ADC clock data recovery

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